Some of computers have implementation of the TLB (Translation Lookaside Buffer). For example, an operating system sets the address translation information to the TLB in order to cache the information. The address translation information is such as a physical address associated with a logical address of each virtual space or a map size.
The TLB exists within a CPU (Central Processing Unit) of the computer and is configured to speed up the translation from the virtual address into the physical address. The TLB has a number of entries and registers, in each entry, the information is stored, which is used for the operating system to perform the translation from the virtual address into the physical address.
If having an access to the virtual address while the CPU executes a command, the CPU searches for the information registered by the operating system in the TLB. Normally, the virtual address is used as a search key, and a physical address associated with the virtual address is returned as a search result. If the information corresponding to the virtual address exists in the TLB, the address translation is executed very quickly, and the CPU accesses the memory by use of the physical address acquired from the TLB. Whereas if the information corresponding to the virtual address does not exist in the TLB, the CPU generates a trap (interrupt) and notifies the operating system that there is no information in the TLB. The operating system receiving the trap registers the information corresponding to the virtual address in the TLB and resubmits the command. When resubmitting the command, the information corresponding to the virtual address is registered in the TLB, and therefore the CPU can access the memory by using the information corresponding to the virtual address.
If the information in the TLB is corrupted due to a fault of the operating system, it follows that the CPU accesses unexpected physical address. The access to the unexpected physical address leads to a possibility of causing a serious problem such as a malfunction of the computer and data corruption. As a matter of fact, there is an instance of causing an erroneous registration of the TLB entry due to the fault of the operating system and further causing hang-up of the system or the malfunction of the program. Therefore, a means for checking the information registered in the TLB of each CPU or a means for checking whether or not a process of the operating system, relating to TLB, runs correctly is desired.
A tool has hitherto been prepared for the purpose of extracting the information for examining a cause of a trouble such as the fault of the operating system and checking the operation (regression test) thereof. For example, it is sufficient for a computer administrator to execute the tool such as an operation checking command in firmware (Service Processor) which manages the computer. On the occasion of executing the operation checking command, the computer administrator designates the CPU as an operation checking target. Through the execution of the operation checking command, the computer administrator can acquire the information registered in the TLB of the designated CPU. For instance, in the case of an UltraSPARC processor system, as the operation checking command prepared in the firmware is started up, the firmware executes an ASI (Address Space Identifiers) command for extracting the TLB information. With the ASI command for extracting the TLB information, the firmware acquires the information registered in the TLB and displays the acquired information to the computer administrator. Details of the ASI command for extracting the information registered in the TLB are described in Chapter 6 of the Manual (UltraSPARC User's Manual Revision 2, July 1997) of the UltraSPARC processor.    [Patent document 1] Japanese National Publication of International Patent Application No. 2007-500401    [Patent document 2] Japanese Laid-open Patent Publication No. 63-273149